1. Field of the Invention
This invention relates to a semiconductor memory equipped with a chip selection signal terminal, and in particular to a semiconductor memory in which the access time as counted from the input of a chip selection signal is reduced.
2. Description of the Related Art
FIG. 6(a) is a block diagram of a conventional semiconductor memory including a memory cell array and a precharger/equalizer which are shown in detail in FIG. 6(b). CSrepresents the chip selection signal which is applied to a selection signal generating circuit 1. The H (High) level of this signal indicates the nonselecting condition, the memory circuit being in the stand-by condition, the inner selection signal CSAbeing at the H level. When signal CSAis at the H level, the operation of an address input buffer circuit 2 is inhibited and the operation of a decoder 4 is halted, keeping the level of the word and column select lines, which constitute the selection lines of memory cell array 6, at their lower level.
CTL is a control signal for circuit operation, controlling the operation of a precharger/equalizer 5 for the data lines for transmitting the data of memory cell array 6 as well as the operations of a data amplifier 7 and an output circuit 8. In the stand-by condition, signal CTL is at the H level, the data lines being precharged and equalized. At the same time, the operation of circuits 7 and 8 is stopped. When the signal CSis at the H level, the signal CSBis at the H level, keeping CTL at the H level. Further, a pulse signal generator 3 is provided so that operation may also be effected when changes occur in the address signals Ai supplied to circuit 2.
FIG. 7 shows concrete circuit examples of the selection signal generator 1, the address input buffer circuit 2 and the pulse signal generator 3. The signal CSAis input to input NOR gates 20 for the address signals, preventing changes in signals Ai from being transmitted to the inside of the circuit when CSAis at the H level. Any change in Ai when CSAis low (L level) is detected by the circuit 3 with respect to the rise and fall of the signal, a pulse signal ATD being generated for each address to perform OR operation of the signals ATD for all the addresses. The signal ATD associated with each address signal Ai (i=o . . . n) is supplied to a respective input device of OR circuit 3-2. When signal CSgoes low, the corresponding drop in CSBis delayed by the delay circuit DB of selection signal generator 1; when CSBdrops to the L (Low) level, a P-channel MOS transistor 3-1 is turned on, causing the OR circuit 3-2 to operate. When CSBis at the H level, P-channel MOS transistor 3-1 is turned off and current is not supplied to OR circuit 3-2.
Next, the operation of the circuit shown in FIG. 6(a) will be described with reference to the timing chart of FIG. 8. When the signal level of CSis changed from the H to the L level, CSAis changed to the L level, an address signal Ai being transmitted to the inside of the circuit through the associated input NOR gate 20. When Ai is at the L level, a change occurs in the inside address signal, generating an ATD pulse. CTL level is lowered at the termination of the ATD pulse; if the Ai's are all at the H level and no ATD pulse is generated, the CTL lowering time does not change since CSBis lowered simultaneously with the ATD pulse lowering. The address signals Ai are transmitted to decoder 4, and the signal level of the word lines and the column select lines which lead to the memory cells to be selected is raised. As is well known, the word lines are connected to the memory cells to select those memory cells which are in the ROW direction. The column select lines select the data lines which are connected to the column of the memory cell to be selected. The information stored in the memory cells then appears on the data lines, and is output to the output terminal through amplifier 7 and output circuit 8.
When an address signal Ai changes while CSremains at the L level, an ATD pulse is generated, causing the CTL to be raised to the H level so that precharging and equalization of the data lines are effected. Readout of data from the next address is then performed.
In conventional semiconductor memories with such a construction as described above, the CSaccess timing when the address signal Ai is at the L level is such that when CSchanges to the L level and the CSAlevel is consequently lowered, the output of the corresponding address input NOR gate 20 changes. In the case of CSaccess, access is started at this time. In the case of address access, the output of NOR gate 20 changes when the address signal Ai changes since CSAis already at the L level, thus starting access. Accordingly, the CSaccess is more delayed than the address access by the time between lowering of CSand the resultant lowering of CSA.
In the case of CSaccess, the data line is already precharged and equalized, access being started in this condition. Accordingly, there is no particular limit to the speed-up of the signal level rise of the word lines and the column select lines; the faster the rise, the better.
It would be advantageous, if, in a conventional semiconductor memory, the CSBdrop could occur at a shorter time after a CSdrop, so that the width of the ATD pulse diminished, thereby speeding up the operation of the address input buffer 2 and of the decoder 4. However, in a conventional semiconductor memory, reducing the width of the ATD pulse results in the pulse width of the CTL being also diminished. In the case of address access, however, there is a danger of the wrong data being written to the memory cell selected next, thereby destroying the stored data, unless the data lines are kept in the reset condition for a sufficient length of time through precharging and equalization by the CTL since the data of the previous cycle remains on the data line. Further, it is not sufficient for the operation of data amplifier 7 and of output circuit 8 to be inhibited for a short period of time by CTL since that will cause amplifier 7 to be operated before the data appears on the data line to a sufficient degree, which will cause malfunctions due to noises, resulting in a delayed access time.
Thus, it has been impossible in conventional semiconductor memories to speed up the CSaccess by diminishing the width of the ATD pulse since that involves the above-mentioned problem at the time of address access.